1. Field of the Invention
The present invention relates to a phase-change memory device, providing nonvolatile memory for FLASH memory, embedded memory, and DRAM. More particularly, a pulse-writing driver circuit for writing data in a phase-change random-access memory (PRAM) array.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as ovonic or chalcogenide memory, is a non-volatile memory device which stores data using a phase-change material, (e.g., chalcogenide amorphous semiconductors, such as Ge—Sb—Tb (GST)). PRAM has all the advantages of a dynamic random access memory (DRAM) and also has non-volatile and low power consumption properties. Phase-change memories use current to heat up a ceramic alloy of germanium, antimony and tellurium: Ge2Sb2Te5, or GST. A bit is represented by changing the phase of the GST chalcogenide material from a resistive amorphous state, referred to as the reset state, to a crystalline state, called the set state.
When a write operation is performed, current that flows through the phase-change material GST, can transform the phase-change material GST into a crystalline (conducting) state or an amorphous (high resistance) state.
Whether the phase-change material GST is transformed into a crystalline state or an amorphous state is determined by the magnitude of current flowing in the phase-change material GST and the timing of that current. When strong current flows in the phase-change material GST for a short period of time, (followed by a rapid quench period) the phase-change material GST is transformed into an amorphous (high resistance) state. The amorphous state is referred to as a reset state and corresponds to data “1”.
When current weaker than the reset current flows in the phase-change material GST for a longer period of time, the phase-change material GST is transformed into a crystalline (conducting) state, which is referred to as a set state and corresponds to data “0”.
FIG. 1 is an equivalent circuit diagram of a PRAM (phase-change random access memory) memory cell.
A PRAM memory cell 100 operates by converting a small volume of the chalcogenide (variable resistor GST) material back and forth between the crystalline and amorphous phases and includes one switch (transistor) TR and one variable resistor GST. The variable resistor is a phase-change material (e.g., Ge—Sb—Tb). A word line WL is connected to control the transistor TR, and a bit line BL is connected to supply current through the phase-change material GST (and through the transistor TR when it is conducting).
The phase-change material GST has the physical property that its resistively is changed by orders of magnitude (e.g., by 103) as it is transformed from an amorphous state to a crystalline state. The phase-change material GST becomes crystalline or amorphous depending on temperature and heating time and cooling (quench) time, so as to store information.
For a phase-change of the phase-change material GST, a temperature higher than 900° C. is generally necessary. The phase-change is achieved by Joule Heating using current applied to the phase-change material (GST resistor) of a memory cell 100.
In a write operation, a GST resistor in a memory cell 100 may be transformed into an amorphous (high resistance) state by performing the steps of: causing write current “i” to flow through the phase-change material (GST resistor), heating the phase-change material (GST resistor) to a melting temperature Tm, and fast quenching the phase-change material GST. Rapid cooling of the material to below its glass transition temperature causes the material to be locked into its amorphous phase. Accordingly, the phase-change material (GST resistor) stores information “1” in its amorphous state. Such an amorphous state is referred to as a reset state.
To switch the phase-change memory element (GST resistor) back to its conductive state, the material is heated to a temperature between the glass transition temperature and the melting temperature, causing nucleation and crystal growth to rapidly occur over a period of several nanoseconds. A GST resistor in a memory cell 100 may be transformed into a crystalline (conducting) state by performing the steps of causing write current “ii” to flow in the phase-change material GST, heating the phase-change material GST to at least a crystallization temperature Tc, maintaining the temperature of the GST material at crystallization temperature Tc for a predetermined period of time (for allowing the formation of crystals in the GST material), and quenching the phase-change material GST. Accordingly, the phase-change material (GST resistor) stores information “0” in a crystalline state. Such a crystalline state is referred to as a set state.
The phase-change material GST becomes crystalline (set) or amorphous (reset) according to data-controlled current supplied from the outside the memory cell 100. The resulting phase-change is dependant upon the magnitude of write-current and the width (duration) of the write-current pulse. Current necessary for amorphousness is called reset current “i” and current necessary for crystallization is called set current “ii”. The magnitude of the reset current “i” is generally greater than the magnitude of the set current “ii”, and the time for applying the reset current “i” is shorter than time for applying the set current “ii”. It is possible to write to the memory device at pulse durations of nanoseconds.
In a read operation, a bit line and a word line are selected and a specific memory cell 100 is selected. Next, current flows from the outside and a voltage potential according to the resistance of the phase-change material GST is measured using a sense-amplifying circuit (not shown), such that the stored information (“1” or “0”) is determined.
FIG. 3 is a block diagram of a conventional pulse-write circuitry for a general write operation in a phase-change memory device.
FIG. 4 is a timing diagram of the pulse-write operation in the phase-change memory device of FIGS. 1 and 3.
Referring to FIG. 3, a word line (WL of FIG. 1) is selected by a row selector 320 which receives a row address, and a bit line (BL of FIG. 1) is selected by a column selector 340 which receives a column address. A phase-change (PRAM) memory cell (100 in FIG. 1) within the array 310 is selected by the word line and the bit line and stores a “1” or a “0” in response to data-controlled current supplied from the outside the memory cell (100).
The pulse-write operation of a conventional phase-change memory device 300 will be described in further detail with reference to signal timing depicted in FIG. 4. A data buffer 350 receiving data DATA generates a write control signal WMDL. The write control signal WMDL has the same logic level as the data DATA.
A control logic 360 responds to control signals /CS, /WE, /UB, /LB, and /OE input from the outside to generate a driver control signal PWD which controls a write-current driver 330. When the driver control signal PWD is a high level, the write-current driver 330 is operated.
The driver control signal PWD has a different pulse width depending upon whether the data DATA is “1” or “0”. This is because time needed to transform the phase-change material GST into a crystalline state is different from time needed to transform the phase-change material GST into an amorphous state as described above.
When the write control signal WMDL is a high level and the driver control signal PWD is a high level, the bit line applies reset current to a memory cell (100) within the phase-change memory (PRAM) array 310. When the write control signal WMDL is a low level and the driver control signal PWD is a high level, the bit line applies set current to the memory cell (100) within the phase-change memory array 310.
As explained above, to store data DATA (e.g., “1” or “0”) in the phase-change memory device, both the writing current and duration of its application will be controlled according to the data DATA to be written.